Encapsulation is of vital importance to power semiconductor chips, which not only plays the role of protecting the chips and enhancing the heat conduction performances, but also provides an interface to communicate the internal worlds of the chips with external circuits. Currently continuous increasing scale of chip manufacture as well as the tremendous and rapidly growing electronic device market drives the growth of the semiconductor encapsulation industry. In order to meet the demands of light weight and compact products, various encapsulation structures are renewed; wherein chip encapsulation methods capable of satisfying the light weight and compact as well as high current density requirement receive more serious considerations.
As shown in FIG. 1, the existing encapsulation of a power semiconductor chip includes pins 1, chip carrier 2, bonding adhesive 3, chip 4, bond wire 5 and a plastic package body 6; wherein the chip carrier 2 and the pins are disconnected at the beginning of the encapsulation process where a gap is kept between the chip carrier 2 and the pins 1. During the encapsulation process of the chip, the chip carrier 2 and the pins 1 are arranged on chip mounting equipment. The bonding adhesive is disposed on the chip carrier 2, and then the chip 4 is pressed on the bonding adhesive 3. The squeezing effect of the chip 4 to the bonding adhesive 3 causes aggravation of the bonding adhesive 3 to overflow to the surrounding area of the chip 4, and the bonding adhesive 3 could even drip down onto the chip mounting equipment from the gap between the chip carrier 2 and the pins 1 to contaminate the chip mounting equipment.
In the existing art of multiple chips co-package, at the beginning of encapsulation process, the chip mounting areas are disconnected from each other in addition to the fact that the chip carrier and the pins are disconnected. A gap is kept between the chip mounting areas. FIG. 2A-2C are schematic cross sections of a metal clip semiconductor encapsulation with multiple chips in prior art. The structure comprises pins 1′, chip carrier 2′ with two chip mounting areas, bonding adhesive 3′, chips 4′ and connection metal clips 5′. As shown in FIG. 2A a gap d1 is kept between the chip mounting areas of chip carrier 2′ and a gap d2 is also kept between the chip carriers 2′ and the pins 1′. As shown in FIG. 2B, when the size of the chips 4′ is increased with the chip carriers 2′ remains the same size, the bonding adhesive 3′ below the chips 4′ could overflow to the edges of the chip carrier 2′. As shown in FIG. 2C, the bonding adhesive 3′ could even flow into the gap between the chip carriers 2′, as well as the gap between the chip carriers 2′ and the pins 1′ to contaminate the chip mounting equipment. Therefore, during actual manufacturing process, in order to avoid the contamination on the chip mounting equipment caused by the overflowing of the bonding adhesive, mounting distance margin requirements are regulated based on different bonding adhesive, representing reducing the area of the chips under the premise of a set encapsulation size, or increasing the encapsulation size under the premise of a fix chip areas. However, the measure greatly reduces the utilization rate of the chip size in the semiconductor encapsulation.